VLSI
8 projects
Digital design projects in Verilog HDL — processors, controllers and RTL modules with simulation and synthesis reports.
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Verilog HDLXilinx VivadoModelSim
Advanced
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner
UART Communication Module Design
Serial UART transmitter/receiver core designed and verified in Verilog
Verilog HDLModelSimFPGA
Intermediate
Vending Machine Controller (FSM in Verilog)
Classic finite state machine design exercise implemented and simulated
Verilog HDLModelSimXilinx Vivado
Beginner
SRAM Memory Controller Design
Read/write memory controller core designed and verified at RTL level
Verilog HDLModelSimXilinx Vivado
Intermediate
Digital Clock with Alarm on FPGA
Real-time digital clock and alarm system implemented on an FPGA board
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner
Pipelined Adder Architecture for High-Speed Arithmetic
Comparative study and RTL implementation of pipelined vs. ripple-carry adders
Verilog HDLXilinx VivadoModelSim
Advanced