VLSI
15 projects
Digital design projects in Verilog HDL — processors, controllers and RTL modules with simulation and synthesis reports.
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
UART Communication Module Design
Serial UART transmitter/receiver core designed and verified in Verilog
Vending Machine Controller (FSM in Verilog)
Classic finite state machine design exercise implemented and simulated
SRAM Memory Controller Design
Read/write memory controller core designed and verified at RTL level
Digital Clock with Alarm on FPGA
Real-time digital clock and alarm system implemented on an FPGA board
Pipelined Adder Architecture for High-Speed Arithmetic
Comparative study and RTL implementation of pipelined vs. ripple-carry adders
Low-Power 4-bit Comparator with Pre/Post-Layout Analysis
Full-custom CMOS comparator design with layout-level power and delay estimation
Clock-Gated D Flip-Flop using Transmission Gate
Transmission-gate-based DFF with clock gating for reduced dynamic power
16-bit Binary Multiplier using Carry Save Adder (CSA)
High-speed multiplier architecture built on carry save addition and synthesized at RTL
Overlapping 10101 Sequence Detector with Low-Power Technique
FSM-based overlapping sequence detector optimized with a low-power design technique
8-bit Carry Look-Ahead Adder (CLA) with Layout Design
High-speed CLA adder with full physical layout and pre/post-layout timing and power analysis
Low-Power 4-bit Adder with Layout Design
Power-optimized 4-bit adder carried through to layout with pre/post delay comparison
4-bit High-Speed BCD Adder using CMOS Technology (PDP Analysis)
CMOS BCD adder verified functionally with delay-vs-power (PDP) trade-off analysis