Back to VLSI
Intermediate
SRAM Memory Controller Design
Read/write memory controller core designed and verified at RTL level
RTL design of an SRAM memory controller handling read/write operations, address decoding and timing control, verified with a comprehensive simulation test bench.
What's included
- Read/write control logic with address decoding
- Timing diagrams for read and write cycles
- Self-checking test bench
- Synthesis and area/timing report
- Full documentation
Tech stack
Verilog HDLModelSimXilinx Vivado
More in VLSI
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Verilog HDLXilinx VivadoModelSim
Advanced
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner