Back to VLSI
Advanced
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Design of a simplified 8-bit RISC processor core including ALU, register file, and control unit, implemented in Verilog HDL and verified through simulation.
What's included
- Custom instruction set architecture (ISA)
- Datapath and control unit design
- Test bench with sample assembly programs
- Simulation waveforms and functional verification
- Detailed architecture report
Tech stack
Verilog HDLXilinx VivadoModelSim
More in VLSI
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner
UART Communication Module Design
Serial UART transmitter/receiver core designed and verified in Verilog
Verilog HDLModelSimFPGA
Intermediate