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Intermediate
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Design and simulation of a low-power Arithmetic Logic Unit using CMOS logic, with power and timing analysis compared against a conventional design.
What's included
- RTL design of ALU with multiple operations
- Power optimization techniques applied and compared
- Functional simulation with test benches
- Synthesis report with area/power/timing metrics
- Full project report and waveform screenshots
Tech stack
Verilog HDLXilinx VivadoModelSimCMOS Design
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