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Intermediate
Overlapping 10101 Sequence Detector with Low-Power Technique
FSM-based overlapping sequence detector optimized with a low-power design technique
A finite state machine that detects the overlapping bit pattern 10101 in a serial input stream, with a suitable low-power technique (such as clock gating) applied and its impact on power quantified.
What's included
- FSM design supporting overlapping pattern detection
- Low-power technique applied with before/after comparison
- Test bench covering overlapping and non-overlapping cases
- Power estimation report
- State diagram and full documentation
Tech stack
Verilog HDLModelSimLow-Power Design Techniques (Clock Gating)
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