Back to VLSI
Intermediate
Clock-Gated D Flip-Flop using Transmission Gate
Transmission-gate-based DFF with clock gating for reduced dynamic power
A D flip-flop built using transmission gate logic with clock gating applied to cut unnecessary switching activity, with performance analyzed against a conventional DFF design.
What's included
- Transmission-gate-based DFF schematic design
- Clock gating logic integrated for power savings
- Performance comparison vs. conventional DFF
- Power, delay and PDP analysis
- Report with schematic and simulation waveforms
Tech stack
Cadence VirtuosoSPICE (HSPICE/LTspice)CMOS TechnologyTransmission Gate Logic
More in VLSI
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Verilog HDLXilinx VivadoModelSim
Advanced
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner