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Intermediate
Low-Power 4-bit Adder with Layout Design
Power-optimized 4-bit adder carried through to layout with pre/post delay comparison
A low-power 4-bit adder circuit designed at the transistor level and laid out physically, with pre-layout and post-layout delay estimated and compared to quantify the impact of parasitics.
What's included
- Low-power 4-bit adder schematic design
- Physical layout with DRC/LVS clean verification
- Pre-layout vs. post-layout delay comparison
- Power estimation at schematic level
- Report with schematic, layout and waveform screenshots
Tech stack
Cadence VirtuosoSPICE (HSPICE/LTspice)CMOS TechnologyLayout (DRC/LVS)
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