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8-bit Carry Look-Ahead Adder (CLA) with Layout Design
High-speed CLA adder with full physical layout and pre/post-layout timing and power analysis
An 8-bit Carry Look-Ahead Adder designed at the transistor level for reduced carry propagation delay, carried through to physical layout, with pre-layout and post-layout delay and power compared.
What's included
- 8-bit CLA schematic design with carry generate/propagate logic
- Physical layout with DRC/LVS clean verification
- Pre-layout vs. post-layout delay and power comparison
- Comparison against ripple-carry delay
- Full report with schematic, layout and analysis
Tech stack
Cadence VirtuosoSPICE (HSPICE/LTspice)CMOS TechnologyLayout (DRC/LVS)
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