Back to VLSI
Advanced
Pipelined Adder Architecture for High-Speed Arithmetic
Comparative study and RTL implementation of pipelined vs. ripple-carry adders
Design and comparison of pipelined adder architectures against traditional ripple-carry adders, analyzing speed and area trade-offs through RTL simulation and synthesis.
What's included
- Multiple adder architectures implemented
- Pipeline stages with timing analysis
- Comparative synthesis report (area/speed)
- Test benches for functional verification
- In-depth technical report
Tech stack
Verilog HDLXilinx VivadoModelSim
More in VLSI
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Verilog HDLXilinx VivadoModelSim
Advanced
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner