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Low-Power 4-bit Comparator with Pre/Post-Layout Analysis
Full-custom CMOS comparator design with layout-level power and delay estimation
A low-power 4-bit magnitude comparator designed at the transistor level, with schematic simulation followed by physical layout, comparing pre-layout and post-layout power and delay figures.
What's included
- Transistor-level schematic design of a 4-bit comparator
- Low-power design technique applied and justified
- Physical layout with DRC/LVS clean verification
- Pre-layout vs. post-layout power and delay comparison
- Full report with schematic, layout and waveform screenshots
Tech stack
Cadence VirtuosoSPICE (HSPICE/LTspice)CMOS TechnologyLayout (DRC/LVS)
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