Back to VLSI
Advanced
16-bit Binary Multiplier using Carry Save Adder (CSA)
High-speed multiplier architecture built on carry save addition and synthesized at RTL
A 16-bit binary multiplier designed using a Carry Save Adder architecture to reduce the critical path compared to a conventional ripple-carry-based multiplier, implemented and synthesized in Verilog.
What's included
- CSA-based multiplier architecture in Verilog
- Synthesis with area/timing report
- Comparison against a conventional array multiplier
- Self-checking test bench with randomized inputs
- Full report with architecture diagrams
Tech stack
Verilog HDLXilinx VivadoModelSim
More in VLSI
Low Power ALU Design using CMOS
Power-optimized Arithmetic Logic Unit implemented and simulated at gate level
Verilog HDLXilinx VivadoModelSimCMOS Design
Intermediate
8-bit RISC Processor Design
Custom instruction-set RISC CPU core designed and simulated in Verilog
Verilog HDLXilinx VivadoModelSim
Advanced
FPGA-Based Traffic Light Controller
Finite state machine controller for a traffic signal, implemented on FPGA
Verilog HDLFPGA (Basys/Nexys)Xilinx Vivado
Beginner