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Intermediate
4-bit High-Speed BCD Adder using CMOS Technology (PDP Analysis)
CMOS BCD adder verified functionally with delay-vs-power (PDP) trade-off analysis
A 4-bit high-speed BCD adder designed using CMOS technology, functionally verified through simulation, with delay and power measured and combined into a Power-Delay Product (PDP) analysis.
What's included
- BCD adder schematic design in CMOS logic
- Functional verification through simulation
- Delay and power measurement across test cases
- Power-Delay Product (PDP) analysis and trade-off discussion
- Full report with schematic and simulation waveforms
Tech stack
Cadence VirtuosoSPICE (HSPICE/LTspice)CMOS Technology
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